US 12,393,258 B1
Wake-up management circuit for multiple processors
Said Bshara, Tira (IL); Dror Fleischmann, Ramat Gan (IL); Erez Izenberg, Tel Aviv-Jaffa (IL); Avigdor Segal, Netanya (IL); Guy Nakibly, Kedumim (IL); and Jonathan Cohen, Hod Hasharon (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/194,287.
Int. Cl. G06F 1/3296 (2019.01); G06F 1/3234 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3278 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a first circuit;
a second circuit; and
at least one data path between the first circuit and the second circuit;
wherein the first circuit includes:
a plurality of processor circuits, the processor circuits being configured to cycle between a low power mode and an active mode; and
a communication fabric coupled between the processor circuits and the at least one data path;
wherein the second circuit includes:
an input/output (I/O) data port;
a memory access circuit coupled to the I/O port; and
a wake-up management circuit coupled between the memory access circuit and the at least one data path, wherein the wake-up management circuit is configured to:
receive a data packet from the memory access circuit;
generate at least one wake-up signal for at least one processor circuit based on the data packet having a destination address associated with the at least one processor circuit; and
provide the at least one wake-up signal to the at least one processor circuit through the communication fabric.