US 12,393,253 B2
Adaptive clock signal frequency scaling
Chunfeng Hu, Singapore (SG); and Rajan Raghvendra, Singapore (SG)
Assigned to MAXLINEAR, INC., Carlsbad, CA (US)
Filed by MAXLINEAR, INC., Carlsbad, CA (US)
Filed on Jan. 9, 2024, as Appl. No. 18/408,548.
Application 18/408,548 is a continuation of application No. 17/806,934, filed on Jun. 14, 2022, granted, now 11,868,194, issued on Jan. 9, 2024.
Application 17/806,934 is a continuation of application No. 16/134,174, filed on Sep. 18, 2018, granted, now 11,360,539, issued on Jun. 14, 2022.
Prior Publication US 2024/0143060 A1, May 2, 2024
Int. Cl. G06F 1/00 (2006.01); G06F 1/08 (2006.01); G06F 1/324 (2019.01); H03K 5/135 (2006.01); G06F 1/3203 (2019.01)
CPC G06F 1/324 (2013.01) [G06F 1/08 (2013.01); H03K 5/135 (2013.01); G06F 1/3203 (2013.01)] 18 Claims
OG exemplary drawing
 
1. Adaptive frequency scaling circuitry having synchronizing dynamic and fixed clock signals, the circuitry comprising:
dynamic clock gating circuitry configured to modulate an input clock signal based on one or more performance values to produce a dynamic clock signal with an adjustable frequency;
fixed clock gating circuitry coupled to the dynamic clock gating circuitry and configured to output a fixed clock signal from the dynamic clock signal, wherein the fixed clock gating circuitry maintains the output of the fixed clock signal when the dynamic clock gating circuitry modulates the input clock signal for causing a frequency change to the adjustable frequency; and
packet processing circuitry including a shared packet buffer, wherein the one or more performance values includes a queue length of the shared packet buffer.