US 12,393,220 B2
Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device
Hiroshi Koshida, Osaka (JP); Shinzo Koyama, Osaka (JP); Tatsuya Kabe, Osaka (JP); and Masaki Tamaru, Kyoto (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Apr. 11, 2023, as Appl. No. 18/299,007.
Application 18/299,007 is a continuation of application No. PCT/JP2021/031083, filed on Aug. 25, 2021.
Claims priority of application No. 2020-179346 (JP), filed on Oct. 27, 2020.
Prior Publication US 2023/0244262 A1, Aug. 3, 2023
Int. Cl. G05F 3/26 (2006.01); G01J 1/44 (2006.01); H10D 84/60 (2025.01)
CPC G05F 3/265 (2013.01) [G01J 1/44 (2013.01); G01J 2001/4466 (2013.01); H10D 84/645 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A substrate current suppression circuit comprising:
a semiconductor substrate of a first polarity, the semiconductor substrate including a first principal surface and a second principal surface on opposite sides;
a first transistor, a second transistor, a third transistor, and a fourth transistor on a first principal surface side of the semiconductor substrate; and
a fixed voltage line that supplies a fixed voltage to a collector of the third transistor and a collector of the fourth transistor, wherein
each of a collector of the first transistor and a collector of the second transistor is connected to a substrate region of the first polarity on a second principal surface side in the semiconductor substrate,
a polarity of the third transistor is opposite to a polarity of the first transistor,
a polarity of the fourth transistor is opposite to a polarity of the second transistor, and
the fixed voltage is a voltage higher than a base voltage of the third transistor and the fourth transistor when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.