US 12,393,219 B2
Stand-by circuit
Sheung Wai Fung, Cambridge (GB); Martin Arnold, Cambridge (GB); Loizos Efthymiou, Cambridge (GB); Tara Vishin, Cambridge (GB); John William Findlay, Cambridge (GB); and Florin Udrea, Cambridge (GB)
Assigned to CAMBRIDGE GAN DEVICES LIMITED, Cambridge (GB)
Filed by Cambridge GaN Devices Limited, Cambridge (GB)
Filed on Oct. 31, 2022, as Appl. No. 17/977,174.
Prior Publication US 2024/0143013 A1, May 2, 2024
Int. Cl. H02M 1/00 (2007.01); G05F 3/26 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC G05F 3/262 (2013.01) [H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 27 Claims
OG exemplary drawing
 
1. A III-nitride power semiconductor based heterojunction device comprising:
a substrate;
a first terminal;
a second terminal;
a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation;
an active heterojunction transistor formed on the substrate, the active heterojunction transistor comprising:
a first III-nitride semiconductor region comprising a first heterojunction comprising an active two-dimensional carrier gas;
a source terminal operatively connected to the III-nitride semiconductor region and further connected to the first terminal;
a drain terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region, the drain terminal operatively connected to the second terminal; and
an active gate region formed over the III-nitride semiconductor region and between the first terminal and the second terminal;
a stand-by signal generation circuit configured to generate a stand-by signal when the input switching signal to the control terminal has not been detected for a set period of time;
at least one Miller clamp transistor and driving circuitry associated with the at least one Miller clamp transistor;
a voltage regulator circuit configured to provide at least a low power consumption output and a high power consumption output, wherein the low power consumption output is enabled at least during the stand-by mode of operation and the high power consumption output is disabled by the stand-by signal during the stand-by mode of operation; and
a rail voltage terminal configured to provide an input to the voltage regulator circuit;
wherein the low power consumption output is provided to the driving circuitry of the at least one Miller clamp transistor to thereby maintain the at least one Miller clamp transistor in an on-state during the stand-by mode of operation; and
wherein the low power consumption output is provided to the stand-by signal generation circuit to thereby power up the stand-by signal generation circuit.