US 12,393,113 B2
Inter-step feedforward process control in the manufacture of semiconductor devices
Roie Volkovich, Hadera (IL); Liran Yerushalmi, Zicron Yaacob (IL); Renan Milo, Rishon Lezion (IL); Yoav Grauer, Haifa (IL); and David Izraeli, Haifa (IL)
Assigned to KLA CORPORATION, Milpitas, CA (US)
Appl. No. 16/770,278
Filed by KLA CORPORATION, Milpitas, CA (US)
PCT Filed May 6, 2020, PCT No. PCT/US2020/031546
§ 371(c)(1), (2) Date Jun. 5, 2020,
PCT Pub. No. WO2021/225587, PCT Pub. Date Nov. 11, 2021.
Prior Publication US 2022/0026798 A1, Jan. 27, 2022
Int. Cl. G05B 19/4099 (2006.01); G03F 1/70 (2012.01)
CPC G03F 1/70 (2013.01) [G05B 19/4099 (2013.01); G05B 2219/45031 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for process control in the manufacture of semiconductor devices comprising:
performing metrology on at least one semiconductor wafer included in a given lot of semiconductor wafers, following processing of said at least one semiconductor wafer by a first processing step, wherein said first processing step is a photoresist development step in which a layer of photoresist is selectively developed on said at least one semiconductor wafer, wherein said metrology comprises measurement of misregistration between said layer of photoresist and another layer of said at least one semiconductor wafer and measurement of other indices associated with said semiconductor wafer, wherein said other indices include reflectivity and pupil indices, and wherein said metrology comprises scatterometry-based type metrology;
performing additional metrology on at least one semiconductor wafer included in an additional lot of semiconductor wafers processed prior to said given lot, said additional metrology being performed following processing of said at least one semiconductor wafer included in said additional lot of semiconductor wafers by said first processing step, wherein said additional metrology comprises measurement of a second misregistration;
generating, based on said metrology on at least one semiconductor wafer included in said given lot and said additional metrology on at least one semiconductor wafer included in said additional lot of semiconductor wafers processed prior to said given lot, at least one correctable to a second processing step subsequent to said first processing step;
adjusting, based on said correctable, performance of said second processing step on at least some other semiconductor wafers of said given lot of semiconductor wafers, wherein said first processing step is different than said second processing step, and wherein said second processing step is an etching step or a cleaning step;
performing metrology following said performance of said second processing step, said adjusting being based on taking into account differences between said metrology following said first processing step and said second processing step, wherein said metrology following said performance of said second processing step comprises measurement of a third misregistration; and
updating said correctable based on said misregistration of said semiconductor wafer and a difference between said second misregistration and said third misregistration.