US 12,392,970 B2
Photonic integrated circuit packaging architectures
Omkar G. Karhade, Chandler, AZ (US); Xiaoqian Li, Chandler, AZ (US); Nitin A. Deshpande, Chandler, AZ (US); Ravindranath Vithal Mahajan, Chandler, AZ (US); Srinivas V. Pietambaram, Chandler, AZ (US); Bharat Prasad Penmecha, Phoenix, AZ (US); and Mitul Modi, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/482,213.
Prior Publication US 2023/0092821 A1, Mar. 23, 2023
Int. Cl. G02B 6/12 (2006.01); G02B 6/42 (2006.01); G02B 6/38 (2006.01)
CPC G02B 6/4239 (2013.01) [G02B 6/4232 (2013.01); G02B 6/4274 (2013.01); G02B 6/4292 (2013.01); G02B 6/3897 (2013.01); G02B 6/4244 (2013.01); G02B 6/4245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A photonic assembly, comprising:
a photonic integrated circuit (PIC) in a first layer including an insulating material, wherein the PIC has an active surface and an opposing backside, and wherein the PIC is embedded in the insulating material with the active surface facing up;
a conductive pillar in the first layer;
an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar;
an optical component optically coupled to the active surface of the PIC; and
a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.