US 12,392,818 B2
Enhanced jet impingement leak prevention for integrated circuit
Ruben Nunez Blanco, Gilbert, AZ (US); Christopher Ackerman, Phoenix, AZ (US); Paul Diglio, Gaston, OR (US); Varun Narayan, Tempe, AZ (US); Craig Yost, Gilbert, AZ (US); Jensen Stenberg, Phoenix, AZ (US); Kelly Lofgreen, Phoenix, AZ (US); Joseph Petrini, Gilbert, AZ (US); and Sami Alelyani, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 29, 2022, as Appl. No. 18/071,399.
Prior Publication US 2024/0175917 A1, May 30, 2024
Int. Cl. G01R 31/28 (2006.01); G01R 31/26 (2020.01); H01L 23/427 (2006.01); H01L 23/467 (2006.01); H01L 23/473 (2006.01)
CPC G01R 31/2877 (2013.01) [G01R 31/2863 (2013.01); H01L 23/467 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit testing apparatus for applying jet impingement to an integrated circuit, the integrated circuit testing apparatus comprising:
an actuator-driven thermal management block comprising seals and an air inlet configured to direct a flow of air into an immediate test environment for an integrated circuit to generate a positive pressure differential with respect to water in an impingement chamber to prevent leakage of the water from the impingement chamber, the impingement chamber formed by the integrated circuit, the actuator-driven thermal management block, and the seals.