US 12,392,814 B2
TEG circuit, semiconductor device, and test method of the TEG circuit
Cheongwon Lee, Suwon-si (KR); Gyosoo Choo, Suwon-si (KR); Youngwoo Park, Suwon-si (KR); Seunghoon Lee, Suwon-si (KR); and Jinwoo Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 23, 2023, as Appl. No. 18/454,404.
Claims priority of application No. 10-2022-0132566 (KR), filed on Oct. 14, 2022.
Prior Publication US 2024/0125841 A1, Apr. 18, 2024
Int. Cl. G01R 31/26 (2020.01)
CPC G01R 31/2607 (2013.01) 20 Claims
OG exemplary drawing
 
1. A test element group (TEG) circuit, comprising:
a first pad configured to receive an applied test voltage;
an amplifier including a first input terminal connected to the first pad, a second input terminal connected to a first terminal of a test transistor, and an output terminal operatively coupled to the second input terminal;
a variable resistor including a first terminal connected to the output terminal of the amplifier and a second terminal connected to the first terminal of the test transistor; and
a gate driving circuit that is configured to supply a gate voltage to a gate of the test transistor.