US 12,389,770 B2
Display panel and display device
Xing Zhang, Beijing (CN); Pan Xu, Beijing (CN); Dacheng Zhang, Beijing (CN); Ying Han, Beijing (CN); Guoying Wang, Beijing (CN); and Yi Chen, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/927,051
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 28, 2021, PCT No. PCT/CN2021/126980
§ 371(c)(1), (2) Date Nov. 22, 2022,
PCT Pub. No. WO2023/070427, PCT Pub. Date May 4, 2023.
Prior Publication US 2024/0334763 A1, Oct. 3, 2024
Int. Cl. H10K 59/80 (2023.01); G09G 3/3208 (2016.01); G09G 3/3266 (2016.01); H10K 59/122 (2023.01); H10K 59/129 (2023.01); H10K 59/131 (2023.01); H10K 59/88 (2023.01)
CPC H10K 59/131 (2023.02) [G09G 3/3208 (2013.01); G09G 3/3266 (2013.01); H10K 59/122 (2023.02); H10K 59/129 (2023.02); H10K 59/80 (2023.02); H10K 59/8722 (2023.02); H10K 59/873 (2023.02); H10K 59/8792 (2023.02); H10K 59/88 (2023.02); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, having a display region, and a dummy pixel region and a circuit region sequentially arranged on at least one side of the display region and in a direction away from the display region, and comprising a base substrate,
wherein the display region has a plurality of display sub-pixels arranged in a plurality of rows and columns, and comprises a pixel driving circuit layer on the base substrate, a planarization layer on a side of the pixel driving circuit layer away from the base substrate, a light-emitting device layer on a side of the planarization layer away from the base substrate, and an encapsulation layer on a side of the light-emitting device layer away from the base substrate, and each of the plurality of the display sub-pixels comprises a pixel driving circuit in the pixel driving circuit layer and a light-emitting device in the light-emitting device layer;
the dummy pixel region comprises a plurality of dummy sub-pixels on the base substrate;
the circuit region comprises a plurality of wires on the base substrate and a frame sealant on a side of the plurality of wires away from the base substrate;
in a direction perpendicular to the base substrate, the frame sealant overlaps with at least a part of the plurality of wires, the encapsulation layer further extends to the circuit region, and overlaps with at least a part of the frame sealant, the planarization layer further extends to the circuit region, and comprises at least one groove in the circuit region, and the at least one groove overlaps with at least a part of the plurality of wires; and
the at least one side comprises a first side and a second side on opposite sides of the display region, the first side and the second side further comprise a binding region on a side of the circuit region away from the display region, the binding region comprises a first binding region on the first side and a second binding region on the second side, the first binding region comprises at least one first chip-on-film, the second binding region comprises at least one second chip-on-film, and the at least one first chip-on-film and the at least one second chip-on-film are centrosymmetric with respect to a center of the display region.