US 12,389,769 B2
Display panel, display device
Binyan Wang, Beijing (CN); Feng Wei, Beijing (CN); Tianyi Cheng, Beijing (CN); and Meng Li, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/914,850
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 10, 2021, PCT No. PCT/CN2021/099487
§ 371(c)(1), (2) Date Sep. 27, 2022,
PCT Pub. No. WO2022/257083, PCT Pub. Date Dec. 15, 2022.
Prior Publication US 2024/0224637 A1, Jul. 4, 2024
Int. Cl. H10K 59/13 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) 20 Claims
OG exemplary drawing
 
1. A display panel, wherein the display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor, a second transistor and a fourth transistor, the second transistor is provided with a first electrode connected to a gate of the driving transistor and a second electrode connected to a second electrode of the driving transistor, the fourth transistor is provided with a first electrode connected to a data line and a second electrode connected to a first electrode of the driving transistor, the driving transistor and the fourth transistor are P-type transistors, the second transistor is an N-type transistor, the display panel further comprises:
a base substrate;
a first conductive layer located at a side of the base substrate and comprising: a first gate line and a first conductive portion, an orthographic projection of the first gate line on the base substrate extending along a first direction, a partial structure of the first gate line being configured to form a gate of the fourth transistor, and the first conductive portion being configured to form the gate of the driving transistor;
a second conductive layer located at the side of the base substrate and comprising a second gate line, an orthographic projection of the second gate line on the base substrate extending along the first direction, and a partial structure of the second gate line being configured to form a first gate of the second transistor, and the orthographic projection of the second gate line on the base substrate being located between an orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the first gate line on the base substrate;
a second conductive portion, an orthographic projection of the second conductive portion on the base substrate at least partially overlapping with the orthographic projection of the first gate line on the base substrate;
a fourth conductive layer located at the side of the base substrate and comprising a first connection portion connected to the first conductive portion and the second conductive portion respectively through a via hole.