US 12,389,767 B2
Display panel and method for manufacturing a display panel having a tiled screen with a fan-out lead region
Lubin Shi, Beijing (CN); Wanpeng Teng, Beijing (CN); Liang Chen, Beijing (CN); Bin Qin, Beijing (CN); Ke Wang, Beijing (CN); Jintao Peng, Beijing (CN); Fangzhen Zhang, Beijing (CN); and Kuanjun Peng, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/783,207
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 20, 2021, PCT No. PCT/CN2021/094894
§ 371(c)(1), (2) Date Jun. 7, 2022,
PCT Pub. No. WO2021/233382, PCT Pub. Date Nov. 25, 2021.
Claims priority of application No. 202010431623.X (CN), filed on May 20, 2020.
Prior Publication US 2023/0013848 A1, Jan. 19, 2023
Int. Cl. H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/18 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02); H10K 59/126 (2023.02); H10K 59/18 (2023.02); H10K 59/1201 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A display panel having a display region and a fan-out lead region, the fan-out lead region being located in the display region;
the display panel comprising:
a base;
a pixel circuit layer disposed on the base and located in the display region, the pixel circuit layer including a plurality of pixel circuits, at least one pixel circuit being located in the fan-out lead region, a pixel circuit including a plurality of transistors, and each transistor having an active layer pattern;
a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, at least one fan-out lead being electrically connected to the pixel circuits; and
an electric field shielding pattern disposed between the pixel circuit layer and a film layer where the plurality of fan-out leads are located, at least orthographic projections of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base being located within an orthographic projection of the electric field shielding pattern on the base, the electric field shielding pattern being configured to be applied with a constant voltage to shield interference signals, from the plurality of fan-out leads, acting on the active layer patterns of the transistors located in the fan-out lead region; and
the display panel further comprising:
connection elements disposed on a side of the base away from the plurality of fan-out leads; and
a plurality of side traces extending from the fan-out lead region to the side of the base away from the plurality of fan-out leads through a side surface of the base, each fan-out lead being electrically connected to a connection element through a side trace; or,
the display panel further comprising:
connection elements disposed on a side of the base away from the plurality of fan-out leads, wherein
the base is provided with a plurality of eighth vias therein, and each fan-out lead is electrically connected to a connection element through an eighth via.