US 12,389,733 B2
Light-emitting diode chip, display substrate and manufacturing method thereof
Junjie Ma, Beijing (CN); Haiwei Sun, Beijing (CN); Yuanda Lu, Beijing (CN); Shanwei Yang, Beijing (CN); Linxia Qi, Beijing (CN); Zhijun Xiong, Beijing (CN); and Jiawei Zhao, Beijing (CN)
Assigned to BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Jun. 4, 2024, as Appl. No. 18/733,213.
Application 18/733,213 is a continuation of application No. 17/417,493, granted, now 12,027,648, previously published as PCT/CN2020/118932, filed on Sep. 29, 2020.
Prior Publication US 2024/0322082 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10H 29/14 (2025.01); H01L 25/075 (2006.01); H10H 20/01 (2025.01); H10H 20/831 (2025.01); H10H 20/857 (2025.01)
CPC H10H 29/142 (2025.01) [H01L 25/0753 (2013.01); H10H 20/01 (2025.01); H10H 20/8312 (2025.01); H10H 20/857 (2025.01); H10H 20/032 (2025.01); H10H 20/0364 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A light-emitting diode chip, comprising:
a first conductive type semiconductor layer;
a light-emitting layer at a side of the first conductive type semiconductor layer;
at least two second conductive type semiconductor layers at a side of the light-emitting layer away from the first conductive type semiconductor layer; and
at least two first electrodes electrically respectively connected with the at least two second conductive type semiconductor layers,
wherein orthographic projections of the at least two second conductive type semiconductor layers on the first conductive type semiconductor layer are spaced apart from each other, and orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are spaced apart from each other,
a planar shape of the first conductive type semiconductor layer is an N-polygon, and the orthographic projections of the at least two first electrodes on the first conductive type semiconductor layer are respectively on perpendicular bisectors of at least two edges of the N-polygon or on corners of the N-polygon, and the at least two edges are uniformly distributed among all edges of the N-polygon,
an orthographic projection of a second electrode on the first conductive type semiconductor layer is at a center of the N-polygon, and N is a positive integer greater than or equal to 3.