US 12,389,718 B2
Method for fabricating a semiconductor device including integrating III-V device and CMOS device, and the semiconductor device thereof
Eugene A. Fitzgerald, Windham, NH (US); Kenneth Eng Kian Lee, Singapore (SG); Cheng Yeow Ng, Singapore (SG); and Fayyaz Moiz Singaporewala, Singapore (SG)
Assigned to NEW SILICON CORPORATION PTE LTD, Singapore (SG)
Appl. No. 17/640,547
Filed by NEW SILICON CORPORATION PTE LTD, Singapore (SG)
PCT Filed Sep. 25, 2020, PCT No. PCT/SG2020/050544
§ 371(c)(1), (2) Date Mar. 4, 2022,
PCT Pub. No. WO2021/061052, PCT Pub. Date Apr. 1, 2021.
Claims priority of provisional application 62/906,986, filed on Sep. 27, 2019.
Prior Publication US 2022/0293820 A1, Sep. 15, 2022
Int. Cl. H10H 20/824 (2025.01); H01L 25/16 (2023.01); H10H 20/833 (2025.01)
CPC H10H 20/824 (2025.01) [H01L 25/167 (2013.01); H10H 20/833 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
(i) forming a III-V semiconductor material layer comprising a substrate layer and a device layer attached to the substrate layer, the device layer having a III-V device comprising a top device electrode layer and a bottom device electrode layer and an active layer formed between the top device electrode layer and the bottom device electrode layer;
(ii) forming an electrically conductive interlayer on the device layer;
(iii) bonding the electrically conductive interlayer to a bottom side of a partially processed CMOS device layer having at least one transistor formed at a top side of the partially processed CMOS device layer; and
(iv) forming a contact plug on each of the top device electrode layer and the bottom device electrode layer of the III-V device, wherein a top surface of each of the contact plugs is approximately co-planar with the at least one transistor, and performing a back-end CMOS process to interconnect the at least one transistor and the III-V device to form an integrated circuit.