US 12,389,675 B2
Semiconductor device having nanosheet transistor and methods of fabrication thereof
Mao-Lin Huang, Hsinchu (TW); Jia-Ni Yu, New Taipei (TW); Lung-Kun Chu, New Taipei (TW); Chung-Wei Hsu, Hsinchu (TW); Chih-Hao Wang, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); and Kuan-Lun Cheng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 3, 2024, as Appl. No. 18/625,282.
Application 18/625,282 is a continuation of application No. 17/883,971, filed on Aug. 9, 2022, granted, now 11,961,840.
Application 17/883,971 is a continuation of application No. 17/105,108, filed on Nov. 25, 2020, granted, now 11,450,664, issued on Sep. 20, 2022.
Prior Publication US 2024/0274604 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/856 (2025.01) [H01L 21/02603 (2013.01); H10D 30/031 (2025.01); H10D 30/0415 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/701 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0181 (2025.01); H10D 84/038 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material;
a high-K (HK) dielectric layer having at least three surfaces in contact with the first intermixed layer;
a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material; and
a third intermixed layer having at least three surfaces in contact with the second intermixed layer, the third intermixed layer comprising a third material having a first polarity,
wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.