US 12,389,670 B2
Air spacer and capping structures in semiconductor devices
Lin-Yu Huang, Hsinchu (TW); Chia-Hao Chang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Chih-Hao Wang, Baoshan Township (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 23, 2023, as Appl. No. 18/158,036.
Application 18/158,036 is a division of application No. 17/006,167, filed on Aug. 28, 2020, granted, now 11,563,001.
Claims priority of provisional application 63/002,036, filed on Mar. 30, 2020.
Prior Publication US 2023/0154921 A1, May 18, 2023
Int. Cl. H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/024 (2025.01); H10D 30/6735 (2025.01); H10D 64/015 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a polysilicon structure on a fin structure;
forming a gate spacer along a sidewall of the polysilicon structure;
forming an epitaxial region on the fin structure;
replacing the polysilicon structure with a gate structure adjacent to the gate spacer;
forming an air spacer between the gate structure and the gate spacer;
forming a spacer seal on the air spacer;
forming, on the gate structure, an air cap comprising etching the gate structure to expose a sidewall of the gate spacer; and
forming a cap seal on the air cap and the spacer seal.