| CPC H10D 84/038 (2025.01) [H01L 21/28123 (2013.01); H10D 30/0243 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/671 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01)] | 20 Claims |
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1. A device comprising:
a semiconductor substrate;
a first gate stack over the semiconductor substrate;
a second gate stack over the semiconductor substrate;
an isolation structure between and contacting the first gate stack and the second gate stack, a first width of an upper portion of the isolation structure is greater than a second width of a lower portion of the isolation structure, the first width and the second width each being measured along a first cross-section perpendicular to a lengthwise dimension of the first gate stack, the first width being measured at a topmost surface of the isolation structure in the first cross-section, and the second width being measured at a bottommost surface of the isolation structure in the first cross-section; and
a first gate spacer on a first sidewall of the isolation structure, wherein a third width of a first upper portion of the first gate spacer is less than a fourth width of a first lower portion of the first gate spacer, the third width and the first width are each being measured along the first cross-section.
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