US 12,389,660 B1
Semiconductor device including backside contact structure with silicide layer formed in FEOL process
Wonkeun Chung, Clifton Park, NY (US); Byounghoon Kim, Rexford, NY (US); Jongjin Lee, Clifton Park, NY (US); and Kang-ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 19, 2024, as Appl. No. 18/808,758.
Claims priority of provisional application 63/631,803, filed on Apr. 9, 2024.
Int. Cl. H10D 30/67 (2025.01); H01L 21/283 (2006.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01)
CPC H10D 64/668 (2025.01) [H01L 21/283 (2013.01); H10D 30/6729 (2025.01); H10D 62/116 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a placeholder structure;
a first silicide layer above a top surface of the placeholder structure along a first direction perpendicular to the top surface and a bottom surface of the placeholder structure;
a first source/drain region above the first silicide layer along the first direction; and
a backside contact structure below the bottom surface of the placeholder structure along the first direction,
wherein the placeholder structure is between a bottom surface of the first silicide layer and a top surface of the backside contact structure along the first direction, and
wherein each of the placeholder structure and the backside contact structure comprises a metal or a metal compound.