US 12,389,645 B2
Semiconductor structure with extended contact structure
Ta-Chun Lin, Hsinchu (TW); Kuo-Hua Pan, Hsinchu (TW); Jhon-Jhy Liaw, Zhudong Township, Hsinchu County (TW); Chao-Ching Cheng, Hsinchu (TW); Hung-Li Chiang, Taipei (TW); Shih-Syuan Huang, Taichung (TW); Tzu-Chiang Chen, Hsinchu (TW); I-Sheng Chen, Taipei (TW); and Sai-Hooi Yeong, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 1, 2024, as Appl. No. 18/429,755.
Application 18/429,755 is a division of application No. 17/666,051, filed on Feb. 7, 2022, granted, now 11,923,413.
Application 17/666,051 is a division of application No. 16/868,625, filed on May 7, 2020, granted, now 11,245,005, issued on Feb. 8, 2022.
Application 16/868,625 is a continuation in part of application No. 16/681,097, filed on Nov. 12, 2019, granted, now 11,183,560, issued on Nov. 23, 2021.
Application 16/681,097 is a continuation of application No. 15/979,123, filed on May 14, 2018, granted, now 10,522,622, issued on Dec. 31, 2019.
Prior Publication US 2024/0170537 A1, May 23, 2024
Int. Cl. H01L 29/76 (2006.01); H01L 21/02 (2006.01); H01L 29/94 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01)
CPC H10D 62/121 (2025.01) [H01L 21/02603 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
nanostructures formed over the substrate, wherein the nanostructures comprise channel regions and source/drain regions, and the channel regions comprise a first channel region and a second channel region;
a gate structure vertically sandwiched the channel regions of the nanostructures, wherein a portion of the gate structure is vertically sandwiched between a bottom surface of the first channel region and a top surface of the second channel region; and
a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.