US 12,389,640 B2
High voltage avalanche diode for active clamp drivers
Henry Litzmann Edwards, Garland, TX (US); Joseph Maurice Khayat, Bedford, NH (US); and Archana Venugopal, Mountain View, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on May 3, 2024, as Appl. No. 18/654,186.
Application 18/654,186 is a division of application No. 17/536,391, filed on Nov. 29, 2021, granted, now 11,984,475.
Prior Publication US 2024/0282812 A1, Aug. 22, 2024
Int. Cl. H10D 62/10 (2025.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01)
CPC H10D 62/108 (2025.01) [H10D 8/00 (2025.01); H10D 8/024 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit comprising:
forming a thin field relief oxide structure in a semiconductor substrate;
forming a shallow N-type well (SNW) in the semiconductor substrate adjacent a first side of the thin field relief oxide structure; and
forming a shallow P-type well (SPW) in the semiconductor substrate adjacent an opposite second side of the thin field relief oxide structure, the SNW and the SPW each having a peak dopant concentration under the thin field relief oxide structure and being spaced apart under the thin field relief oxide structure by the semiconductor substrate.