US 12,389,637 B2
Nonvolatile semiconductor memory device including a memory cell
Megumi Ishiduki, Yokkaichi Mie (JP); Hiroshi Nakaki, Yokkaichi Mie (JP); and Takamasa Ito, Nagoya Aichi (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 13, 2023, as Appl. No. 18/537,954.
Application 18/537,954 is a continuation of application No. 17/825,542, filed on May 26, 2022, granted, now 11,888,041.
Application 17/825,542 is a continuation of application No. 17/009,373, filed on Sep. 1, 2020, granted, now 11,380,770, issued on Jul. 5, 2022.
Application 17/009,373 is a continuation of application No. 16/130,432, filed on Sep. 13, 2018, granted, now 10,797,144, issued on Oct. 6, 2020.
Claims priority of application No. 2018-055371 (JP), filed on Mar. 22, 2018.
Prior Publication US 2024/0120395 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 99/00 (2023.01); H10D 84/00 (2025.01)
CPC H10D 30/696 (2025.01) [H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/50 (2023.02); H10D 30/0413 (2025.01); H10D 30/693 (2025.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H10B 41/20 (2023.02); H10B 41/27 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 99/00 (2023.02); H10D 84/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising:
an underlying insulating layer provided above a substrate;
a source layer provided above the underlying insulating layer, the source layer including a conductive part and a semiconductor part above the conductive part;
a stacked body provided above the source layer, the stacked body including a plurality of first electrode layers and a plurality of first insulating layers interposed between two of the first electrode layers adjacent in a stacking direction respectively; and
a first columnar part piercing through the stacked body in the stacking direction, a lower end portion of the first columnar part being electrically connected to the source layer,
the first columnar part having a first width in a first direction perpendicular to the stacking direction inside the semiconductor part and a second width in the first direction inside a lowermost first insulating layer of the first insulating layers, the first width being larger than the second width.