| CPC H10D 30/6711 (2025.01) [H10D 30/0321 (2025.01)] | 10 Claims |

|
1. A transistor comprising:
a source and a drain each implemented in a first type active region;
a gate implemented relative to the source and the drain;
a body implemented in the first type active region and substantially covered by the gate;
a body tie implemented in a second type active region; and
a connecting portion that connects the body tie to the body, the connecting portion and the gate dimensioned such that the connecting portion is only underneath a respective portion of the gate and the respective portion of the gate is only over the connecting portion.
|