US 12,389,631 B2
Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Tokyo (JP); Jun Koyama, Kanagawa (JP); Hiroyuki Miyake, Kanagawa (JP); Kei Takahashi, Kanagawa (JP); Kouhei Toyotaka, Kanagawa (JP); Masashi Tsubuku, Kanagawa (JP); Kosei Noda, Kanagawa (JP); and Hideaki Kuwabara, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Nov. 29, 2023, as Appl. No. 18/522,543.
Application 15/372,493 is a division of application No. 13/799,246, filed on Mar. 13, 2013, granted, now 9,666,678, issued on May 30, 2017.
Application 18/522,543 is a continuation of application No. 17/010,151, filed on Sep. 2, 2020, granted, now 11,837,461.
Application 17/010,151 is a continuation of application No. 16/121,700, filed on Sep. 5, 2018, granted, now 10,777,682, issued on Sep. 15, 2020.
Application 16/121,700 is a continuation of application No. 15/372,493, filed on Dec. 8, 2016, granted, now 10,074,747, issued on Sep. 11, 2018.
Application 13/799,246 is a continuation of application No. 12/904,565, filed on Oct. 14, 2010, granted, now 8,421,068, issued on Apr. 16, 2013.
Claims priority of application No. 2009-238885 (JP), filed on Oct. 16, 2009.
Prior Publication US 2024/0243204 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 86/40 (2025.01); G06K 19/077 (2006.01); H01L 23/66 (2006.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/84 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01); G11C 7/00 (2006.01); G11C 19/28 (2006.01); H02M 3/07 (2006.01)
CPC H10D 30/6706 (2025.01) [G06K 19/07758 (2013.01); H01L 23/66 (2013.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 84/0163 (2025.01); H10D 84/038 (2025.01); H10D 84/84 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01); G11C 7/00 (2013.01); G11C 19/28 (2013.01); H01L 2223/6677 (2013.01); H02M 3/07 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor over a substrate having an insulating surface, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided and a first gate electrode layer;
a second transistor over the substrate, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided and a second gate electrode layer; and
a first conductive layer electrically connected to the first oxide semiconductor layer,
wherein the first gate electrode layer is over the first oxide semiconductor layer,
wherein the second gate electrode layer is over the second oxide semiconductor layer,
wherein a first insulating layer is provided between the first oxide semiconductor layer and the insulating surface, where the first insulating layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein a second conductive layer is provided between the first insulating layer and the insulating surface, where the second conductive layer overlaps the channel formation region in the first oxide semiconductor layer,
wherein the first insulating layer is between the second oxide semiconductor layer and the insulating surface, where the first insulating layer overlaps the channel formation region in the second oxide semiconductor layer,
wherein no conductive layer which overlaps the channel formation region in the second oxide semiconductor layer is provided between the first insulating layer and the insulating surface,
wherein a channel length of the first transistor is longer than a channel length of the second transistor,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the first gate electrode layer, the second gate electrode layer, and the first conductive layer are provided on a same layer and comprise a same material.