US 12,389,630 B2
Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern
Kyung-Eun Byun, Seongnam-si (KR); Sangwon Kim, Seoul (KR); Changhyun Kim, Seoul (KR); Keunwook Shin, Yongin-si (KR); and Changseok Lee, Gwacheon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 17, 2022, as Appl. No. 17/697,400.
Claims priority of application No. 10-2021-0121173 (KR), filed on Sep. 10, 2021.
Prior Publication US 2023/0081960 A1, Mar. 16, 2023
Int. Cl. H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/63 (2025.01) [H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 64/252 (2025.01); H10D 64/514 (2025.01)] 19 Claims
OG exemplary drawing
 
15. A vertical channel transistor comprising:
a first source/drain electrode;
a second source/drain electrode spaced apart from the first source/drain electrode in a first direction;
a first channel pattern between the first source/drain electrode and the second source/drain electrode;
a first gate electrode on a side surface of the first channel pattern;
a first gate insulation layer between the first channel pattern and the first gate electrode;
a first graphene insertion layer between the first source/drain electrode and the first channel pattern;
a second channel pattern provided opposite the first channel pattern across first gate electrode; and
a second gate insulation layer between the first gate electrode and the second channel pattern,
wherein the first channel pattern and the second channel pattern are in a region where the first source/drain electrode and the second source/drain electrode face each other in the first direction.