US 12,389,629 B2
Source/drain regions in integrated circuit structures
Sean T. Ma, Portland, OR (US); and Cory E. Weber, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 3, 2020, as Appl. No. 16/891,950.
Prior Publication US 2021/0384307 A1, Dec. 9, 2021
Int. Cl. H01L 29/417 (2006.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01)
CPC H10D 30/6219 (2025.01) [H10D 30/62 (2025.01); H10D 30/6757 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first channel region including a first semiconductor material;
a second channel region including a second semiconductor material; a
a source/drain region between the first channel region and the second channel region, wherein the source/drain region includes a first semiconductor region proximate to the first channel region, a second semiconductor region proximate to the second channel region, a third semiconductor region, and a contact metal at least partially between the first semiconductor region and the second semiconductor region;
a dielectric layer that is physically in contact with the third semiconductor region; and
a substrate,
wherein the first semiconductor region is between a portion of the contact metal and the first channel region, the second semiconductor region is between the portion of the contact metal and the second channel region, the first semiconductor region abuts a first surface of the contact metal, the second semiconductor region abuts a second surface of the contact metal, the first surface and the second surface of the contact metal are opposing, the third semiconductor region is between the first semiconductor region and the second semiconductor region, and the dielectric layer is between the contact metal and the substrate.