US 12,389,628 B2
Semiconductor devices and methods of manufacturing thereof
Shih-Yao Lin, New Taipei (TW); Hsiao Wen Lee, Hsinchu (TW); Li-Jung Kuo, Hsinchu (TW); Chen-Ping Chen, Toucheng Township (TW); and Ming-Ching Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 3, 2024, as Appl. No. 18/732,022.
Application 18/066,777 is a division of application No. 17/230,414, filed on Apr. 14, 2021, granted, now 11,552,195, issued on Jan. 10, 2023.
Application 18/732,022 is a continuation of application No. 18/066,777, filed on Dec. 15, 2022, granted, now 12,027,624.
Prior Publication US 2024/0332422 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6211 (2025.01) [H10D 30/024 (2025.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of first non-planar semiconductor structures disposed in a first area of a substrate, wherein the first non-planar semiconductor structures, parallel with one another, are separated with a first distance; and
a first isolation region collectively embedding a lower portion of each of the first non-planar semiconductor structures and comprising a first layer and a second layer, wherein the second layer is disposed above the first layer, and wherein at least the second layer of the first isolation region is in a cured state.