US 12,389,626 B2
High-voltage transistor with self-aligned isolation
Walid M. Hafez, Portland, OR (US); and Chia-Hong Jan, Portland, OR (US)
Assigned to Intel Corproation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 1, 2020, as Appl. No. 16/889,610.
Application 16/889,610 is a continuation of application No. 15/754,151, granted, now 10,707,346, previously published as PCT/US2015/052204, filed on Sep. 25, 2015.
Prior Publication US 2020/0295190 A1, Sep. 17, 2020
Int. Cl. H10D 30/60 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 30/62 (2025.01)
CPC H10D 30/603 (2025.01) [H10D 62/116 (2025.01); H10D 62/156 (2025.01); H10D 64/017 (2025.01); H10D 30/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a fin-shaped semiconductor body, the fin-shaped semiconductor body comprising silicon;
a trench isolation region having a first side, a second side, a bottom, an upper portion and a lower portion, the upper portion above the fin-shaped semiconductor body and the lower portion in the fin-shaped semiconductor body, the lower portion defining a first portion of the fin-shaped semiconductor body and a second portion of the fin-shaped semiconductor body;
a first gate spacer along at least part of the first side of the trench isolation region, the first gate spacer having a bottom above the bottom of the trench isolation region;
a second gate spacer along at least part of the second side of the trench isolation region, the second gate spacer having a bottom above the bottom of the trench isolation region;
a gate electrode over the first portion of the fin-shaped semiconductor body, the gate electrode having a first side and a second side;
a third gate spacer along the first side of the gate electrode; and
a fourth gate spacer along the second side of the gate electrode.