| CPC H10D 30/472 (2025.01) [H10D 30/015 (2025.01); H10D 64/117 (2025.01); H10D 64/605 (2025.01); H10D 64/661 (2025.01); H10D 64/671 (2025.01)] | 19 Claims |
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1. A semiconductor device comprising:
an active region above a substrate, the active region comprising at least two material layers with different band gaps, wherein the active region comprises a channel layer and a barrier layer disposed on the channel layer;
source and drain electrodes in contact with the active region;
a gate above the active region, the gate is laterally between the source and drain electrodes, the gate has an upper surface;
a polysilicon layer above the substrate, the polysilicon layer has a lower surface, wherein the polysilicon layer is positioned laterally adjacent to the gate and the lower surface of the polysilicon layer is substantially coplanar with the upper surface of the gate; and
a silicide layer on the polysilicon layer.
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