US 12,389,620 B2
Split-gate trench MOS transistor with self-alignment of gate and body regions
Davide Giuseppe Patti, Mascalucia (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Dec. 16, 2021, as Appl. No. 17/553,477.
Claims priority of application No. 102020000032771 (IT), filed on Dec. 30, 2020.
Prior Publication US 2022/0208995 A1, Jun. 30, 2022
Int. Cl. H10D 30/01 (2025.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H01L 21/765 (2006.01)
CPC H10D 30/0297 (2025.01) [H01L 21/2253 (2013.01); H01L 21/2652 (2013.01); H01L 21/26586 (2013.01); H10D 30/668 (2025.01); H10D 62/393 (2025.01); H10D 64/117 (2025.01); H01L 21/765 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A process for manufacturing an integrated device including at least one MOS transistor integrated on a die of semiconductor material of a first type of conductivity having a main surface, the process comprising:
forming one or more gate trenches extending from the main surface into the die;
coating the gate trenches with an electrically insulating material to obtain corresponding coated internal portions of the gate trenches being coated with corresponding separation insulating layers;
filling the coated internal portions of the gate trenches with electrically conductive material forming corresponding field plates;
forming a layer of electrically insulating material in the gate trenches to obtain corresponding splitting insulating layers of electrically insulating material on the field plates and corresponding coated upper portions of the gate trenches that are coated with corresponding gate insulating layers;
forming an auxiliary insulating layer of electrically insulating material on the gate insulating layers and the splitting insulating layers to obtain a passing insulating layer and a blocking insulating layer, respectively;
implanting dopants of a second type of conductivity into the die from the main surface along one or more implantation directions being tilted with respect to the main surface, the dopants being implanted selectively by passing though the passing insulating layer in an implantation zone at the gate insulating layers and being blocked by the blocking insulating layer in a blocking zone at the splitting insulating layers;
diffusing the dopants being implanted to form a body region;
removing the auxiliary insulating layer after the implanting of the dopants; and
filling the coated upper portions of the gate trenches with electrically conductive material forming corresponding gate regions thereby being substantially self-aligned in depth from the main surface with the body region, surfaces of the gate regions being coplanar with the main surface.