US 12,389,619 B2
Semiconductor device structure with inner spacer layer
Han-Yu Lin, Nantou County (TW); Chansyun David Yang, Shinchu (TW); Fang-Wei Lee, Hsinchu (TW); Tze-Chung Lin, Hsinchu (TW); Li-Te Lin, Hsinchu (TW); and Pinyen Lin, Rochester, NY (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 26, 2024, as Appl. No. 18/616,449.
Application 17/504,104 is a division of application No. 16/299,531, filed on Mar. 12, 2019, granted, now 11,152,491, issued on Oct. 19, 2021.
Application 18/616,449 is a continuation of application No. 18/182,774, filed on Mar. 13, 2023, granted, now 11,973,129.
Application 18/182,774 is a continuation of application No. 17/504,104, filed on Oct. 18, 2021, granted, now 11,605,728, issued on Mar. 14, 2023.
Claims priority of provisional application 62/721,931, filed on Aug. 23, 2018.
Prior Publication US 2024/0234549 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/01 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/0243 (2025.01) [H01L 21/0214 (2013.01); H01L 21/02167 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/31116 (2013.01); H01L 21/32105 (2013.01); H01L 21/3211 (2013.01); H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a gate stack wrapping around a plurality of nanowire structures, wherein the gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures;
a gate spacer layer along a sidewall of the first portion of the gate stack; and
a plurality of inner spacer layers along sidewalls of the second portions of the gate stack, wherein the gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.