| CPC H10D 30/024 (2025.01) [H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |
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1. A method, comprising:
forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip;
forming a gate structure over the semiconductor layers;
etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure;
forming epitaxial layers in the recesses, respectively;
forming isolation layers over the epitaxial layers, respectively;
forming epitaxial source/drain structures over the isolation layers, respectively;
performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layers, and one of the isolation layers, wherein one of the epitaxial source/drain structures is exposed through the via opening; and
forming a backside via in the via opening.
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