US 12,389,616 B2
Transistors with multiple silicide layers
Man Gu, Malta, NY (US); Hong Yu, Clifton Park, NY (US); Jianwei Peng, Clifton Park, NY (US); and Haiting Wang, Clifton Park, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Feb. 11, 2022, as Appl. No. 17/669,584.
Prior Publication US 2023/0261088 A1, Aug. 17, 2023
Int. Cl. H10D 30/01 (2025.01); H01L 21/285 (2006.01); H10D 30/67 (2025.01)
CPC H10D 30/0213 (2025.01) [H01L 21/28518 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure for a transistor, the structure comprising:
a first dielectric spacer;
a second dielectric spacer;
a gate laterally between the first dielectric spacer and the second dielectric spacer, the gate including a first silicide layer extending from the first dielectric spacer to the second dielectric spacer;
a second silicide layer embedded within the first silicide layer, the second silicide layer extending to a depth in the first silicide layer, and the second silicide layer laterally positioned between a first portion of the first silicide layer and a second portion of the first silicide layer; and
a first contact that is aligned to the second silicide layer.