| CPC H10D 12/481 (2025.01) [H10D 8/411 (2025.01); H10D 62/127 (2025.01); H10D 62/393 (2025.01)] | 8 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate including an IGBT region having an IGBT element and a FWD region having an FWD element, the semiconductor substrate having a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region, the semiconductor substrate having a first surface adjacent to the base layer and a second surface opposite to the first surface and adjacent to the collector layer and the cathode layer;
a gate insulating film disposed on a wall surface of each of a plurality of gate trenches disposed in the semiconductor substrate in the IGBT region, each of the plurality of gate trenches passing through the base layer to reach the drift layer and extending in one direction as a longitudinal direction along a planar direction of the semiconductor substrate, the plurality of gate trenches being arranged in an arrangement direction that intersects with the longitudinal direction;
a gate electrode disposed on the gate insulating film;
a first conductivity type emitter region disposed in a surface layer portion of the base layer in the IGBT region to be in contact with each of the gate trenches, the emitter region having a higher impurity concentration than the drift layer;
a second conductivity type contact region disposed in the base layer in the IGBT region, the contact region having a higher impurity concentration than the base layer;
a first electrode disposed adjacent to the first surface of the semiconductor substrate, the first electrode being electrically connected to the base layer and the emitter region;
a second electrode disposed adjacent to the second surface of the semiconductor substrate, the second electrode being electrically connected to the collector layer and the cathode layer; and
a first conductivity type barrier region disposed above the drift layer in the IGBT region, the barrier region having a higher impurity concentration than the drift layer, wherein
the semiconductor substrate is formed with a contact trench between adjacent gate trenches in the IGBT region, the contact trench having a bottom surface closer to the first surface of the semiconductor substrate than the barrier region is to the first surface,
the first electrode is embedded in the contact trench,
the semiconductor device further comprising:
a first conductivity type connecting region between the bottom surface of the contact trench and the barrier region in the IGBT region, the connecting region being connected to the barrier region and the first electrode and having a higher impurity concentration than the drift layer, wherein
the emitter region and the contact region are arranged in a direction different from the arrangement direction.
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