US 12,389,614 B2
Semiconductor device and method of manufacturing semiconductor device
Shingo Kabutoya, Tsukuba (JP)
Assigned to KYOCERA Corporation, Kyoto (JP)
Appl. No. 17/911,929
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Mar. 18, 2021, PCT No. PCT/JP2021/011210
§ 371(c)(1), (2) Date Sep. 15, 2022,
PCT Pub. No. WO2021/200238, PCT Pub. Date Oct. 7, 2021.
Claims priority of application No. 2020-062399 (JP), filed on Mar. 31, 2020.
Prior Publication US 2023/0137811 A1, May 4, 2023
Int. Cl. H10D 8/01 (2025.01); H01L 21/285 (2006.01); H10D 8/60 (2025.01); H10D 64/64 (2025.01)
CPC H10D 8/051 (2025.01) [H01L 21/28537 (2013.01); H10D 8/605 (2025.01); H10D 64/64 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer in which a trench has been formed;
an insulating film covering an inner surface of the trench;
an electric conductor embedded in the trench covered with the insulating film; and
a Schottky barrier layer forming a Schottky barrier junction together with a surface of the semiconductor layer adjacent to the trench,
wherein the Schottky barrier junction and the Schottky barrier layer are positioned lower than an upper end of the insulating film covering the inner surface of the trench;
wherein an upper surface electrode is formed above and in direct contact with the top surface of the electric conductor and the Schottky barrier layer.