US 12,389,611 B2
Structure and method for forming capacitors for a three-dimensional NAND
Liang Chen, Hubei (CN); Cheng Gan, Hubei (CN); Wei Liu, Hubei (CN); and Shunfu Chen, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 15, 2022, as Appl. No. 17/695,220.
Application 17/695,220 is a division of application No. 16/729,818, filed on Dec. 30, 2019, granted, now 11,437,464.
Application 16/729,818 is a continuation of application No. PCT/CN2019/095069, filed on Jul. 8, 2019.
Prior Publication US 2022/0208960 A1, Jun. 30, 2022
Int. Cl. H10D 1/00 (2025.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 1/68 (2025.01)
CPC H10D 1/043 (2025.01) [H01L 21/76224 (2013.01); H01L 23/528 (2013.01); H01L 23/642 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 1/716 (2025.01); H01L 2225/06548 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional capacitor for a memory device, comprising:
forming, on a first side of a first substrate, a peripheral circuitry comprising a plurality of peripheral devices, a first interconnect layer, a well and, after forming the well, forming a first capacitor electrode, wherein the first capacitor electrode is electrically connected with the well from the first side of the first substrate;
forming, on a second substrate, a memory array comprising a plurality of memory cells and a second interconnect layer;
bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array, such that at least one peripheral device of the peripheral circuitry is electrically connected with at least one memory cell of the memory array;
forming, on a second side of the first substrate, one or more trenches extending completely through the well, wherein the first and second sides are opposite sides of the first substrate;
disposing a capacitor dielectric layer on sidewalls of the one or more trenches;
forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches; and
forming a second capacitor electrode on the capacitor contacts on the second side of the first substrate.