US 12,389,610 B2
Memory device with memory strings using variable resistance memory regions
Ryu Ogiwara, Yokohama Kanagawa (JP); Daisaburo Takashima, Yokohama Kanagawa (JP); and Takahiko Iizuka, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 29, 2022, as Appl. No. 17/877,714.
Application 17/877,714 is a division of application No. 16/908,880, filed on Jun. 23, 2020, abandoned.
Claims priority of application No. 2019-116756 (JP), filed on Jun. 24, 2019.
Prior Publication US 2022/0367568 A1, Nov. 17, 2022
Int. Cl. H10B 63/00 (2023.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/30 (2023.02) [G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10N 70/253 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8822 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of first memory cells each including:
a first variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate;
a first semiconductor layer extending in the first direction and being in contact with the first variable resistance memory region; and
a first insulating layer extending in the first direction and being in contact with the first semiconductor layer,
wherein the first memory cells are connected in series along the first direction, and an air layer is provided inside the first variable resistance memory region;
a plurality of first word lines each extending in a second direction that is orthogonal to the first direction and being in contact with the first insulating layer;
a first select transistor including:
a second semiconductor layer extending in the first direction; and
a second insulating layer extending in the first direction and being in contact with the second semiconductor layer,
wherein one end of the first select transistor is coupled to one end of an uppermost one of the first memory cells in the first direction, and the first select transistor and the first memory cells form a first memory cell string;
a first select gate line extending in the second direction and being in contact with the second insulating layer;
a first bit line extending in a third direction that is orthogonal to each of the first direction and the second direction, the first bit line being coupled to the other end of the first select transistor; and
a source line extending in the second direction and the third direction, the source line being coupled to one end of a lowermost one of the first memory cells in the first direction,
wherein, during a read operation to a selected one of the first memory cells connected to a selected one of the first word lines:
at a first timing:
a first voltage is supplied to the selected one of the first word lines;
a second voltage is supplied to remaining ones of the first word lines other than the selected one of the first word lines;
a third voltage lower than the first voltage and the second voltage is supplied to the first select gate line;
a fourth voltage is supplied to the first bit line; and
the fourth voltage is supplied to the source line,
at a second timing after the first timing:
a fifth voltage lower than the first voltage is supplied to the selected one of the first word lines, and
at a third timing after the second timing:
a sixth voltage different from the fourth voltage is supplied to one of the first bit line and the source line.