US 12,389,601 B2
Three dimensional semiconductor memory device and method for fabricating the same
Sang-Yong Park, Suwon-si (KR); and Jintaek Park, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 1, 2024, as Appl. No. 18/430,189.
Application 18/430,189 is a continuation of application No. 17/726,637, filed on Apr. 22, 2022, granted, now 11,925,023.
Application 17/726,637 is a continuation of application No. 16/939,858, filed on Jul. 27, 2020, granted, now 11,315,948, issued on Apr. 26, 2022.
Application 16/939,858 is a continuation of application No. 15/813,556, filed on Nov. 15, 2017, granted, now 10,727,246, issued on Jul. 28, 2020.
Application 15/813,556 is a continuation of application No. 15/047,392, filed on Feb. 18, 2016, granted, now 9,825,053, issued on Nov. 21, 2017.
Application 15/047,392 is a continuation of application No. 14/800,322, filed on Jul. 15, 2015, granted, now 9,269,722, issued on Feb. 23, 2016.
Application 14/800,322 is a continuation of application No. 14/255,170, filed on Apr. 17, 2014, granted, now 9,087,738, issued on Jul. 21, 2015.
Application 14/255,170 is a continuation of application No. 13/231,177, filed on Sep. 13, 2011, granted, now 8,704,293, issued on Apr. 22, 2014.
Claims priority of application No. 10-2010-0092578 (KR), filed on Sep. 20, 2010.
Prior Publication US 2024/0172444 A1, May 23, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 89/10 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 23/5283 (2013.01); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02); H10D 30/0413 (2025.01); H10D 30/693 (2025.01); H10D 64/037 (2025.01); H10D 89/10 (2025.01); H01L 2924/0002 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor device, comprising:
a substrate including a cell array region and a connection region; and
a stacked structure including a plurality of conductive layers vertically stacked on the substrate, the stacked structure having a first staircase in a first direction on the connection region, a second staircase in a second direction on the connection region, and a third staircase in a third direction, the first, second, and third directions being parallel to a top surface of the substrate, the second direction being perpendicular to the first direction, and the third direction being opposite the first direction,
wherein the first staircase includes first steps that increase by a first height along the first direction,
wherein the second staircase includes second steps that increase by a second height along the second direction, the second height different from the first height, and
wherein the third staircase includes third steps that increase by a third height along the third direction, the third height different from the first height and the second height.