| CPC H10B 43/27 (2023.02) [H01L 23/481 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, alternately spaced apart from each other and stacked in a vertical direction, perpendicular to an upper surface of a substrate;
a plurality of first separation patterns passing through the stack structure in the vertical direction and extending in a first direction, parallel to the upper surface of the substrate;
a plurality of channel structures passing through the stack structure in the vertical direction between a pair of first separation patterns of the plurality of first separation patterns; and
a second separation pattern extending between the pair of first separation patterns in the first direction, and passing through at least one upper gate electrode including an uppermost gate electrode, among the plurality of gate electrodes, in the vertical direction,
wherein the plurality of channel structures include a first channel structure spaced apart from the second separation pattern and a second channel structure having an upper region contacting the second separation pattern,
wherein the first channel structure includes a first core insulating layer, a first channel layer covering an outer side surface of the first core insulating layer, and a first gate dielectric layer covering an outer side surface of the first channel layer,
wherein the second channel structure includes a second core insulating layer, a second channel layer covering an outer side surface of the second core insulating layer, and a second gate dielectric layer covering an outer side surface of the second channel layer,
wherein the first gate dielectric layer includes a first tunneling layer, a first data storage layer, and a first blocking layer, sequentially arranged from the outer side surface of the first channel layer to the plurality of gate electrodes,
wherein the second gate dielectric layer includes a second tunneling layer, a second data storage layer, and a second blocking layer, sequentially arranged from the outer side surface of the second channel layer to the plurality of gate electrodes, wherein, in a plan view, parallel to the upper surface of the substrate, each of the second tunneling layer, the second data storage layer, the second blocking layer, and the second channel layer, in the upper region of the second channel structure, has end portions spaced apart from each other, and
wherein in the plan view, the end portions of the second channel layer are recessed away from end portions of at least one of the second tunneling layer, the second data storage layer, and the second blocking layer in a second direction parallel to the upper surface of the substrate and different from the first direction; and
a plurality of bit lines disposed on the stack structure,
wherein the plurality of bit lines include:
a first bit line electrically connected to the first channel layer of the first channel structure, and extending in the second direction; and
a second bit line electrically connected to the second channel layer of the second channel structure, and extending in the second direction.
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