US 12,388,712 B2
In-network multicast operations
Robert Pawlowski, Beaverton, OR (US); Vincent Cave, Hillsboro, OR (US); Shruti Sharma, Hillsboro, OR (US); Fabrizio Petrini, Menlo Park, CA (US); Joshua B. Fryman, Corvallis, OR (US); and Ankit More, San Mateo, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 13, 2021, as Appl. No. 17/473,540.
Claims priority of provisional application 63/142,664, filed on Jan. 28, 2021.
Prior Publication US 2021/0409265 A1, Dec. 30, 2021
Int. Cl. H04L 41/0893 (2022.01); H04L 41/0803 (2022.01); H04L 41/0895 (2022.01); H04L 41/40 (2022.01); H04L 43/20 (2022.01)
CPC H04L 41/0893 (2013.01) [H04L 41/0803 (2013.01); H04L 41/0895 (2022.05); H04L 41/40 (2022.05); H04L 43/20 (2022.05)] 26 Claims
OG exemplary drawing
 
13. A system comprising:
a system on chip (SoC) comprising:
a group of switch nodes;
a register;
a first group of core nodes to couple with the group of switch nodes; and
a second group of core nodes to couple with the group of switch nodes, wherein:
a core node of the first group of core nodes includes circuitry to execute a single instruction of an instruction set architecture (ISA) that indicates a configuration for a multicast operation,
a switch node of the group of switch nodes includes circuitry to execute one or more message passing instructions based on the configuration,
the configuration is accessed from the register,
the configuration indicates output ports for data multicast through nodes in the group of switch nodes, and
the configuration identifies one of multiple at least one path of the data through the group of switch nodes to two or more endpoint core nodes.