| CPC H04L 9/30 (2013.01) [H04L 9/088 (2013.01)] | 22 Claims |
|
1. A digital communication system comprising:
a network of electronic apparatuses, which comprises plural electronic apparatuses, wherein,
M of the said plural electronic apparatuses are the first to M-th inspection devices, at least one of the other among the said plural electronic apparatuses is an inspector, the said first to M-th inspection devices are the first to M-th peripheral devices, respectively,
the said inspector inputs the first challenge to the said first to M-th peripheral devices,
the said first to M-th peripheral devices respectively return the first to M-th responses to the said inspector in response to the said first challenge according to the response function,
the said first to M-th responses form the first response set, which comprises the said first to M-th responses,
the said inspector stores the said first challenge and the said first response set,
the said first to M-th peripheral devices respectively generate the pairs of the first to M-th secret keys and the first to M-th public keys using the said first to M-th responses,
the said first to M-th peripheral devices respectively comprise the first to M-th integrated circuit (IC) chips,
the said response function has the arguments, the said first challenge as well as the specific random numbers that are respectively specific to the said first to M-th IC chips, and respectively generates the said first to M-th responses,
if an external electronic apparatus, which does not have the said first to M-th IC chips, and the said first peripheral device communicate, the said inspector notices to the said first peripheral device that the said external electronic apparatus has not been authenticated or terminates the communication between the said first peripheral device and the said external electronic apparatus,
wherein, one of the first to M-th IC chips is chosen as the n-th IC chip,
the said n-th IC chip has cell array, row decoder, peripheral controller, code generator, specific inner memory, and external input-output, wherein,
the said cell array is divided into the first and second cell arrays,
the said row decoder is divided into the first and second row decoders, wherein,
the said first and second row decoders respectively control access to the said first and second cell arrays,
the said peripheral controller receives the code of retrieving redundancy mode and the said challenge from the said external input-output, controls the said first and second row decoders based on the said code of retrieving redundancy mode, forwards the said challenge to the said code generator, retrieves the n-th specific random number from the access to the said first and second cell arrays based on the n-th redundancy code stored in the said specific inner memory, and forwards the said n-th specific random number to the said code generator,
the said code generator uses the said response function, generates the n-th response using the said first challenge and the said n-th specific random number, and forwards the said n-th response to the external input-output,
the said external input-output receives input of the said code of retrieving redundancy mode and the said first challenge from the external, receives the said n-th response from the said code generator, and outputs the said n-th response to the external of the said n-th IC chip,
wherein, the said code of retrieving redundancy mode has the setting option of authentication, the mode of indicating exclusive bit, the access option, and the operation option, wherein,
the said cell array is divided into plural subblocks,
the said IC chip, further, has the table of cell block addresses,
the said table of cell block addresses is the correspondence table of an arbitrary address on the said cell array and a set of a subblock address and an inner address inside a subblock,
the said mode of indicating exclusive bit has an indicated bit address as an argument,
the said indicated bit address is an exclusive authentication bit inside the said subblock,
the said setting option of authentication comprises authentication mode and non-authentication mode,
the said exclusive authentication bit is selected as a selected bit address inside the said subblock if the said authentication mode is chosen,
a bit other than the said exclusive authentication bit is selected as a selected bit address inside the said subblock if the said non-authentication mode is chosen,
the said access option controls the set of the said column decoder and the said first and second row decoders, and instructs access to each bit address on the said cell array,
the said operation option has those of write, erase and read at the said each of bit address,
the said peripheral controller reads the said n-th specific random number from the said cell array, based on the said n-th redundancy code, by switching the set of the said access option and the said operation option, if the said authentication mode is chosen.
|