US 12,388,548 B2
Holdover mode device, method and measurement and adjustment module
Che-Cheng Kung, Hsinchu (TW); and Yu-Lun Lo, Hsinchu (TW)
Assigned to FIBER LOGIC COMMUNICATIONS, INC., Hsinchu (TW)
Filed by FIBER LOGIC COMMUNICATIONS, INC., Hsinchu (TW)
Filed on May 10, 2023, as Appl. No. 18/314,959.
Prior Publication US 2024/0297726 A1, Sep. 5, 2024
Int. Cl. H04J 3/06 (2006.01)
CPC H04J 3/0623 (2013.01) [H04J 3/0617 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A holdover mode device, comprising:
a digital phase lock loop (PLL), configured to lock an output clock (OUT[n]) thereof to be an input clock (IN[n]) thereof, and to transmit the output clock (OUT[n]) to at least one hardware module;
a measurement and adjustment module, electrically connected to the digital PLL or a time synchronization source; and
an adjustable oscillator, electrically connected to the measurement and adjustment module, configured to adjust a reference clock (CLK[n]) generated by the adjustable oscillator according to an adjustment signal;
wherein when the time synchronization source is not abnormal, the digital PLL is configured to use the time synchronization source as the input clock (IN[n]) thereof, and the measurement and adjustment module is configured to calculate a variation of a frequency difference between the time synchronization source and the reference clock (CLK[n]), and to build a frequency difference prediction model according to the variation of the frequency difference;
wherein when the time synchronization source is abnormal, the digital PLL is configured to use a buffered time synchronization source as the input clock (IN[n]) thereof, and the measurement and adjustment module is configured to use the frequency difference prediction model to calculate a predicted variation of the frequency difference according to multiple buffered frequency difference values, and to generate the adjustment signal according to the predicted variation of the frequency difference;
wherein the predicted variation of the frequency difference comprises multiple predicated frequency difference values in at least next 8 to 24 hours, and in a holdover mode, in the at least next 8 to 24 hours, a difference between a drift of the output clock (OUT[n]) and the time synchronization source is within 1500 nanoseconds.