US 12,388,466 B2
Method and apparatus for testing error correcting code (ECC) function of FPGA on-chip block random access memory (BRAM)
Jingxiang Wang, GuangZhou (CN); Yue Han, GuangZhou (CN); Zheng Wang, GuangZhou (CN); Yunjie Fan, GuangZhou (CN); Tianping Wang, GuangZhou (CN); Niu Li, GuangZhou (CN); and Qi Zhou, GuangZhou (CN)
Assigned to GOWIN Semiconductor Corporation, Ltd., GuangZhou (CN)
Filed by GOWIN Semiconductor Corporation, GuangZhou (CN)
Filed on Feb. 9, 2024, as Appl. No. 18/438,380.
Prior Publication US 2024/0275406 A1, Aug. 15, 2024
Int. Cl. H03M 13/01 (2006.01); G11C 29/08 (2006.01)
CPC H03M 13/015 (2013.01) [G11C 29/08 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A system for testing Error Correcting Code (“ECC”) function of Field Programmable Gate Array (“FPGA”) on-chip block random access memory (“BRAM”), comprising:
a set on a programmable array logic in the FPGA;
one or more control modules coupled to the FPGA;
at least two BRAMs with ECC function; and
one or more parity bit comparison modules corresponding to each of the BRAMs, wherein the at least two BRAMs are sequentially connected to form a ring connection structure, wherein each parity bit comparison module is connected to its corresponding BRAM and next adjacent BRAM; wherein, the control module is configured to send data read and write test instructions to each BRAM,
wherein each BRAM is configured to sequentially read test data preset in each memory address in the BRAM according to the data read and write test instruction, write the test data into the corresponding memory address of the next BRAM adjacent to the BRAM itself whenever the test data in the memory address is read, and send the first parity bit generated during reading the test data to the parity bit comparison module corresponding to the BRAM, and
wherein each parity bit comparison module is used to obtain the first parity bit generated when the BRAM corresponding to itself reads test data and a second parity bit generated when the next adjacent BRAM writes test data, and compares whether the first parity bit is the same as the second parity bit.