US 12,388,439 B2
Semiconductor integrated circuit and electronic apparatus
Masaru Hirai, Tokyo (JP)
Assigned to MITSUMI ELECTRIC CO., LTD., Tokyo (JP)
Filed by Masaru Hirai, Tokyo (JP)
Filed on Apr. 5, 2024, as Appl. No. 18/627,937.
Claims priority of application No. 2023-080974 (JP), filed on May 16, 2023.
Prior Publication US 2024/0388286 A1, Nov. 21, 2024
Int. Cl. G06F 1/24 (2006.01); H03K 17/22 (2006.01)
CPC H03K 17/223 (2013.01) [G06F 1/24 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a plurality of terminals including a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
a first detection circuit configured to assert a first signal in response to detecting a voltage drop at the first input terminal;
a second detection circuit configured to assert a second signal in response to detecting an overvoltage of the first input terminal;
a third detection circuit configured to assert a third signal in response to detecting a voltage drop at the second input terminal;
a first output circuit configured to monitor the first signal and the second signal, and output a first reset signal from the first output terminal in response to asserting the first signal or the second signal; and
a second output circuit configured to monitor the third signal, and output a second reset signal from the second output terminal in response to asserting the third signal.