US 12,388,059 B2
Chip package structure and chip packaging method
Tonglong Zhang, Shenzhen (CN); Xiaodong Zhang, Shenzhen (CN); Yong Guan, Shanghai (CN); and Heng Li, Shanghai (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Nov. 19, 2021, as Appl. No. 17/531,133.
Application 17/531,133 is a continuation of application No. PCT/CN2019/087659, filed on May 20, 2019.
Prior Publication US 2022/0077123 A1, Mar. 10, 2022
Int. Cl. H01L 25/04 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/568 (2013.01); H01L 23/29 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure comprising:
a carrier board comprising a first circuit;
a second chip comprising a second active layer;
a first chip disposed between the second chip and the carrier board and comprising a first active layer, wherein the first active layer is opposite to the second active layer;
a first interconnection structure disposed between the first chip and the second chip and configured to directly couple the first active layer to the second active layer, wherein the first interconnection structure is formed on a first surface of the first active layer or the second active layer;
a first conductor pillar disposed in the first chip and comprising:
a first end coupled to the first active layer; and
a second end passing through the first chip to couple to the first circuit; a second conductor pillar coupled to the second active layer and the first circuit; and
a dielectric insulating layer disposed on a second surface that is of the first chip and that is facing away from the second chip.