US 12,388,049 B2
High connectivity device stacking
Kurtis Leschkies, San Jose, CA (US); Han-Wen Chen, Cupertino, CA (US); Steven Verhaverbeke, San Francisco, CA (US); Giback Park, San Jose, CA (US); Kyuil Cho, Santa Clara, CA (US); Jeffrey L. Franklin, Albuquerque, NM (US); and Wei-Sheng Lei, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jul. 27, 2023, as Appl. No. 18/360,749.
Application 18/360,749 is a division of application No. 17/578,271, filed on Jan. 18, 2022, granted, now 11,742,330.
Application 17/578,271 is a division of application No. 16/814,785, filed on Mar. 10, 2020, granted, now 11,257,790, issued on Feb. 22, 2022.
Prior Publication US 2024/0021582 A1, Jan. 18, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H05K 1/14 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/49586 (2013.01); H01L 23/5226 (2013.01); H01L 25/50 (2013.01); H05K 1/144 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a first printed circuit board (PCB) comprising:
a first glass fiber reinforced epoxy resin material; and
a first electrical distribution layer formed on the first glass fiber reinforced epoxy resin material;
a second PCB comprising:
a second glass fiber reinforced epoxy resin material; and
a second electrical distribution layer formed on the second glass fiber reinforced epoxy resin material; and
a device spacer interposed between the first PCB and the second PCB to facilitate a physical space therebetween, the device spacer further comprising:
a frame having a first surface opposite a second surface, the frame further comprising:
a frame material comprising a polymer-based dielectric material having ceramic filler particles; and
a via comprising a via surface that defines an opening extending through the frame from the first surface to the second surface, the via having a first diameter of about 10 μm and about 150 μm;
an electrical interconnection disposed within the via on the via surface to form at least part of a conductive path extending between at least a portion of the first and second electrical distribution layers; and
solder bumps conductively coupling the electrical interconnection with the first and second electrical distribution layers.