US 12,388,047 B2
Integrated fan-out platform and manufacturing method for semiconductor devices
Li-Hsien Huang, Zhubei (TW); Hsueh-Lung Cheng, Hsinchu (TW); Yao-Chun Chuang, Hsinchu (TW); and Yinlung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Hsinchu (TW)
Filed on Aug. 23, 2022, as Appl. No. 17/893,354.
Prior Publication US 2024/0071998 A1, Feb. 29, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0655 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/96 (2013.01); H01L 25/18 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/06134 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/16258 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device assembly comprising:
a first die having a first side, a first area on the first side and a second area on the first side;
a second die having a second side, a third area on the second side and a fourth area on the second side;
a plurality of first electrically conductive vias electrically contacting and extending away from the first side of the first die in the first area, each of the first vias having a first size;
a plurality of second electrically conductive vias electrically contacting and extending away from the first side of the first die in the second area, each of the second vias having a second size, the second size being greater than the first size;
a plurality of third electrically conductive vias electrically contacting and extending away from the second side of the second die in the third area, each of the third vias having a third size;
a plurality of the fourth electrically conductive vias electrically contacting and extending away from the second side of the second die in the fourth area, each of the fourth vias having a fourth size, the fourth size being greater than the third size; and
a silicon interconnection die disposed on the first and second sides of the first and second dies respectively, wherein the silicon interconnection die overlaps the first and second areas on the first side of the first die and the third and fourth areas on the second side of the second die and the silicon interconnection die is electrically connected such that electrical signals are selectively exchangeable between the first and second dies through at least one or more of the plurality of first vias, the plurality of second vias, the plurality of third vias and the plurality of fourth vias.