US 12,388,026 B2
Electronic package with rotated semiconductor die
Yao-Chun Su, Hsinchu (TW); Chih-Jung Hsu, Hsinchu (TW); Yi-Jou Lin, Hsinchu (TW); and I-Hsuan Peng, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Oct. 24, 2023, as Appl. No. 18/383,466.
Application 18/383,466 is a continuation of application No. 17/553,760, filed on Dec. 16, 2021, granted, now 11,830,820.
Application 17/553,760 is a continuation of application No. 16/846,381, filed on Apr. 12, 2020, granted, now 11,222,850, issued on Jan. 11, 2022.
Claims priority of provisional application 62/848,064, filed on May 15, 2019.
Prior Publication US 2024/0055358 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/58 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/5385 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 23/66 (2013.01); H01L 25/0655 (2013.01); H01L 2223/6638 (2013.01); H01L 2223/6666 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a base of a rectangular shape;
a chip package comprising a first interface circuit die and a second interface circuit die in proximity to the first interface circuit die, wherein the first interface circuit die and second interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a same molding compound, wherein the chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle; and
a metal ring mounted on the top surface of the base, wherein the metal ring comprises an extension portion completely covering a triangular region between the metal ring and a side of the rotated chip package for warpage control, wherein the extension portion does not overlap with the first interface circuit die or the second interface circuit die.