US 12,388,001 B2
Electronic package
Yu-Lin Shih, Kaohsiung (TW); and Chih-Cheng Lee, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/460,053.
Prior Publication US 2023/0061843 A1, Mar. 2, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49833 (2013.01) [H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/73 (2013.01); H01L 2224/73204 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a low-density circuit structure;
a high-density circuit structure disposed over the low-density circuit structure;
a first underfill disposed over the low-density circuit structure, and extending along a lateral surface of the high-density circuit structure; and
a polymer layer disposed on the lateral surface of the high-density circuit structure, and spaced apart from the first underfill,
wherein the high-density circuit structure comprises a circuit layer including an inner via, and the inner via tapers away from the low-density circuit structure,
wherein in a cross section, the polymer layer has a first bottom surface facing the low-density circuit structure, and the high-density circuit structure has a second bottom surface facing the low-density circuit structure and a circuit layer including a portion protruding beyond the second bottom surface, wherein the portion of the circuit layer has a bottom surface facing the low-density circuit structure and a lateral surface connecting the bottom surface of the portion of the circuit layer, wherein the first underfill contacts the lateral surface of the portion of the circuit layer, wherein the first bottom surface of the polymer layer and an inner portion of the first underfill under the first bottom surface collectively define a gap overlapping the lateral surface of the portion of the circuit layer in a first direction parallel with a top surface of the low-density circuit structure.