US 12,387,813 B2
Method and system for detecting memory error, and device
Bosco Chun Sang Lai, Shenzhen (CN)
Assigned to KINGTIGER Testing Technology (SZ) Ltd., Shenzhen (CN)
Filed by KINGTIGER Testing Technology (SZ) Ltd., Shenzhen (CN)
Filed on Oct. 11, 2023, as Appl. No. 18/485,277.
Claims priority of application No. 202211659866.4 (CN), filed on Dec. 23, 2022.
Prior Publication US 2024/0212783 A1, Jun. 27, 2024
Int. Cl. G11C 29/56 (2006.01)
CPC G11C 29/56008 (2013.01) [G11C 29/56004 (2013.01); G11C 2029/5604 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for detecting a memory error, comprising:
taking an application platform as a test engine of a memory test device, the application platform being provided with a system memory;
capturing, by the memory test device, a data flow of an actual application program of the application platform on a memory transmission line in a manner comprising a logic analyzer; and
taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device, thereby reproducing a memory error of the application platform or the application program on the memory test device, wherein
the data flow comprises at least a command, and the command comprises at least a read command and a write command;
when the write command on the memory transmission line is captured, the taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device comprises:
transmitting, by the memory test device, the captured write command to a transmission line of the tested memory device according to a data writing address, a data writing sequence and a data writing time sequence of the application platform for testing; and recording, by the logic analyzer embedded into the memory test device, a data transmission process;
when the read command on the memory transmission line is captured, the taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device comprises:
transmitting, by the memory test device, the read command and a data reading address captured from the application platform to the transmission line of the tested memory device according to a captured sequence and a captured time sequence;
receiving, by the memory test device, response data of the application platform for the read command and response data of the tested memory device for the read command; and
comparing stored information in the two sets of the response data, determining that the tested memory device has an error if the stored information is inconsistent, and recording error information;
after the capturing, by the memory test device, a data flow of an actual application program of the application platform on a memory transmission line in a manner comprising a logic analyzer, the method further comprises:
storing, by the memory test device, the data flow in a circular buffer region; and
after the taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device, the method further comprises:
stopping, by the memory test device, updating the circular buffer region and a pointer of the circular buffer region when detecting that the tested memory device has an error, and recording a present error node and historical data of the circular buffer region.