US 12,387,811 B2
Semiconductor memory device including an on-die ECC engine
Yujung Song, Suwon-si (KR); Sungrae Kim, Suwon-si (KR); Gilyoung Kang, Suwon-si (KR); Hyeran Kim, Suwon-si (KR); and Chisung Oh, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 24, 2023, as Appl. No. 18/174,186.
Claims priority of application No. 10-2022-0089304 (KR), filed on Jul. 20, 2022; and application No. 10-2022-0128271 (KR), filed on Oct. 7, 2022.
Prior Publication US 2024/0029808 A1, Jan. 25, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/46 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
an on-die error correction code (ECC) engine including a first latch and a second latch; and
a control logic circuit configured to control the on-die ECC engine,
wherein the control logic circuit is configured to set the semiconductor memory device to a test mode in response to a first mode register set command from an external device, and
wherein the on-die ECC engine, in the test mode, is configured to perform operations comprising:
cutting off an electrical connection with the memory cell array;
receiving test data and a write command from the external device;
storing the test data in the first latch;
performing an ECC decoding on the test data stored in the first latch and a test parity data stored in the second latch in response to a read command from the external device; and
providing the external device with a severity signal based on a result of the ECC decoding, wherein the severity signal indicates whether the test data and the test parity data include at least one error bit and indicates whether the at least one error bit is correctable,
wherein the control logic circuit is configured to exit from the test mode in response to a second mode register set command from the external device applied after the read command, and
wherein the second mode register set command is received after the severity signal is transmitted.