US 12,387,809 B2
Method for optimizing flash memory chip and related apparatus
Jun Yu, Dongguan (CN); Guoyu Wang, Chengdu (CN); You Li, Chengdu (CN); and Yongyao Li, Shenzhen (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Aug. 24, 2023, as Appl. No. 18/455,031.
Application 18/455,031 is a continuation of application No. PCT/CN2022/073186, filed on Jan. 21, 2022.
Claims priority of application No. 202110220794.2 (CN), filed on Feb. 26, 2021.
Prior Publication US 2023/0402121 A1, Dec. 14, 2023
Int. Cl. G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/12015 (2013.01); G11C 29/46 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for monitoring and retraining of a non-volatile flash interface (NFI), comprising:
after completing write training of the NFI and establishing a data strobe signal (DQS) trigger pointdetermining whether a trigger condition for monitoring the NFI is met, wherein the DQS trigger point triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to working environmental data of the NFI;
upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes the margin test; and
upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI,
wherein the DQS trigger point divides a cycle of the write DQ into a period before the DQS trigger point as a setup time of the write DQ and a period after the DQS trigger point as a hold time of the write DQ.